Laboratory for Future Interdisciplinary Research of Science and Technology (FIRST) at Tokyo Institute of Technology (Tokyo Tech), Japan

Biography: Dr. Takayuki Ohba is a Professor in Laboratory for Future Interdisciplinary Research of Science and Technology (FIRST) at Tokyo Institute of Technology (Tokyo Tech) from 2013 and The University of Tokyo from 2004 to 2013, respectively. Prior to joining academia, Dr. Ohba was worked at semiconductor department of Fujitsu Limited from 1984 after Non-aqueous Solution Chemical Laboratories at Tohoku University. In Fujitsu Limited, he developed metallization and interconnects processes using chemical vapor deposition (CVD) for various refractory metals. Particularly, W and TiN CVD using various reduction chemistries were distinguish achievement being commercially used in the semiconductor manufacturing. In the1990’s, he was in charge of total integration of multi-level interconnects including Cu and low-k dielectrics. Developed 90-nm MPU was 25% higher performance in the worldwide and applied to the server computer SPARC64 VTM in 2004.
Prof. Ohba is conducting global alliance so-called WOW Alliance and three-dimensional integration (3DI) for the post-scaling since 2007 at The University of Tokyo. WOW Alliance consists industries and academia based on semiconductor supply chain. Prof. Ohba developed the bump-free (no bump) interconnects and ultra-thinning of 300-mm wafer down to 5 micrometer technologies for the application of memory-memory and memory-logic 3D stack. Device characteristics such DRAM and MPU at ~2 micrometer were unveiled by defect and yield analyses in Tokyo Tech. His basic interest is production-worthy wafer level 3D process (WOW and COW) to achieve ultra-small Tera-scale devices with high energy efficiency and low cost. In addition, for the interdisciplinary research, bio-platelets generation, cooling device, and closed rice plant are developing in the alliance. Prof. Ohba has contributed more than 100 papers through these studies. He is a member of the JAP, IEICE, IEEE, EDS, MRS, IMAPS, and committee of MAM, AMC, and ADMETA, respectively. He received his Ph.D. degree from Tohoku University (Electrical Communication) in 1995.

Speech Title: Three Dimensional Stack Process for Tera-Byte DRAM Application using WOW Technology
Abstract: Wafer-on-Wafer (WOW) technology for three-dimensional (3D) integration is discussed. The developed WOW process is referred to as stacking back-to-face after thinning, in which any number of thinned 300-mm wafers and/or heterogeneous dies can be integrated. This wafer stacking method is compatible with multilevel metallization in the back-end-of-line (BEOL), as if replacing dielectrics layers to thinned wafers. WOW process is implemented for three-dimensional (3D) semiconductor integration to realize Tera-byte memory capacity with high energy efficiency. Back-to-face wafer stacking using bumpless (no bump) interconnects enables ultra-thinning of wafer because of no needs micro-bumps for wafer stacking. For instance, wafer thickness using micro-bump is limited at an approximately 50 micrometer to maintain mechanical strength of thinned wafer. Furthermore, a gap comes from bump height 20 to 30 micrometer, between wafers has to fill out using organic material so-called under-fill material. Under-fill material causes thermal stress due to CTE (coefficient of thermal expansion) mismatch of Silicon and thermal resistance for Joule heat of devices. By using bumpless WOW process, wafers and adhesive layer are thinned down to ~2 micrometer, respectively. They provide the shorter less than 1/10 vertical interconnects length and 1/10 thermal resistance compared to conventional bump structure.