Biography: Hiroshi Watanabe was born in Gunnma, Japan. He received the B. Sc, M. Sc., and Ph.D. degrees from the University of Tsukuba, Ibaraki, Japan, in 1989, 1991, and 1994, respectively, all in physics. He joined the Corporate Research& Development Center, Toshiba Corporation from 1994 to 2010. His current position is a tenure-track faculty full professor, Department of Electrical and Computer Engineering (ECE) & Microelectronics and Information System Research Center (MISRC) in National Chiao Tung University (NCTU), Hsinchu, Taiwan, since February, 2010. He has studied theoretical physics, semiconductor device physics, electron devices reliability issues, semiconductor device modeling, and some cutting edge electron devices from theory to experiments. In particular, he had been engaged in the reliability study of NAND Flash, SOI devices, MOSFETs, which are related to local traps in dielectrics. He has also developed a specialized device simulator for gate stack characterization for CMOS devices and flash memory reliability (in particular, NAND Flash) study while he had worked for Toshiba’s Headquarter RD Center. His current research interest is semiconductor securities devices, electronic biosensing, and several fundamental topics related to nano-electronics and their applications. He has more than 100 granted patents all over the world. He is a Senior Member of the IEEE since 2012.
Speech Title: CMOS-Based Batteryless Electron Timer
Abstract: A semiconductor timing device will be reviewed, which comprises plurality of floating gate cell transistors to be manufactured in a standard CMOS process. The first issue in timing precision is a trap-related phenomena through tunnel oxide between floating gate and silicon surface. In order to resolve it, a trap-free cell is necessary to be monitored among plurality of cell transistors. This can be realized by an artful circuit.